JUNE 19–23, 2016

Presentation Details

Name: Next-Generation Memory Systems: Reliability Challenges & Solution Directions
Time: Monday, June 20, 2016
04:20 pm - 04:40 pm
Room:   Panorama 2
Messe Frankfurt
Speaker:   Sparsh Mittal, ORNL
Abstract:   Ongoing process scaling and push for performance have led to increasingly severe reliability challenges for memory systems. For example, process variation (PV)--deviation in parameters from their nominal specifications--threatens to slow down and even pause technological scaling and addressing it is important for continuing the benefits of chip miniaturization. In this talk, I will present a brief background on memory reliability challenges, viz., PV and soft-errors, along with their impact on systems ranging from embedded systems to supercomputers. Then, several architectural strategies for managing PV in different processor components (e.g., core, cache and main memory) and memory technologies (e.g., SRAM, embedded DRAM, DRAM and non-volatile memory) will be discussed. I will also present strategies for managing soft-errors in HPC systems and processor components.