|Name:||Application Performance on Intel Xeon Phi – Being Prepared for KNL & Beyond|
|Time:||Thursday, June 23, 2016
09:00 am - 06:00 pm
|Breaks:||11:00 am - 11:30 am Coffee Break|
01:00 pm - 02:00 pm Lunch
04:00 pm - 04:30 pm Coffee Break
|Organizer:||Richard Gerber, NERSC|
|Kent Milfeld, TACC|
|Chris Newburn, Intel|
|Thomas Steinke, ZIB|
|Abstract:||The workshop will bring together software developers and technology experts to share challenges, experiences and best-practice methods for the optimization of HPC workloads on the Intel Xeon Phi. The workshop will cover application performance and scalability challenges at all levels - from single processor, to moderately-scaled cluster, up to large HPC configurations with many Xeon Phi devices. The keynote will present recent information about the KNL processor. The submitted talks will present the experience from users with early access to KNL and cover optimization and scalability topics in real-world HPC applications, e.g. data layouts and code restructuring for efficient SIMD operation, work distribution and thread management. Aspects related to KNL features (e.g. High-Bandwidth Memory) are of particular interest. The usability of tools for development, debugging and performance analysis will be covered. The panel session provides an opportunity to discuss optimization strategies for Phi and to provide feedback to the toolchain developers.
Application developers on many-core platforms, experts in code optimization for Xeon Phi platform, decision makers for future system deployments.
For more details, please visit the workshop webpage at https://www.ixpug.org/events/ixpug-isc-2016